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Problem Report Number 1384 Submitter's Classification Test Suite problem State Resolved Resolution Test Suite Deficiency (TSD) Problem Resolution ID TSD.X.0666 Raised 1970-01-01 08:00 Updated 2003-03-13 08:00 Published 1996-09-16 08:00 Product Standard Internationalised System Calls and Libraries Extended (UNIX 95) Certification Program The Open Brand certification program Test Suite VSU version 4.1.0 Test Identification CAPIbase/fsetrlimit 26 Problem Summary TSD4U.00151 This test may fail due to timeout on some implementations. Problem Text
This assertion is failing for reasons similar to that in req.U.00310
Here is the journal entries which is produced after I increase the
coefficient of MAX_TIME_TO_RUN on lines 159 & 238 of fsetrlimit26.c
if ((status = wait_for(pid, 6*MAX_TIME_TO_RUN)) = -1
from 6 to 300.
It is clear from the timestamps in the journal that the MAX_TIME_TO_FAIL
hardcoded in the test suite are not sufficient on our implementation.
We request a TSD be granted for this assertion.
400|0 26 1 14:58:21|IC Start
200|0 1 14:58:21|TP Start
520|0 1 4521998 1 1|SPEC1170TESTSUITE CASE 26
520|0 1 4521998 1 2|If the implementation does not inhibit enforcement of
520|0 1 4521998 1 3|limits for the resource RLIMIT_AS:
520|0 1 4521998 1 4|When the size of the stack for the calling process
520|0 1 4521998 1 5|causes the size of the total available memory for the
520|0 1 4521998 1 6|calling process to exceed the limit set by a call to
520|0 1 4521998 1 7|int setrlimit(int resource, const struct rlimit *rlp)
520|0 1 4521998 1 8|for resource RLIMIT_AS and the process is blocking or
520|0 1 4521998 1 9|ignoring SIGSEGV, or is catching SIGSEGV and has not
520|0 1 4521998 1 10|made arrangements to use an alternate stack, the
520|0 1 4521998 1 11|disposition of SIGSEGV shall be set to SIG_DFL before
520|0 1 4521998 1 12|it is generated.
520|0 1 1376263 1 1|PREP: Fork a child
520|0 1 393233 1 1|PREP: Save the current limits
520|0 1 393233 1 2|TEST: Set limits with setrlimit
520|0 1 393233 1 3|INFO: Raise succeeded
520|0 1 393233 1 4|PREP: Set up a signal handler for SIGSEGV
520|0 1 393233 1 5|TEST: The signal disposition was set to SIG_DFL
520|0 1 393233 1 6| before delivery
520|0 1 458769 1 1|PREP: Save the current limits
520|0 1 458769 1 2|TEST: Set new limits
520|0 1 458769 1 3|PREP: Set SIGSEGV to SIG_IGN
520|0 1 458769 1 4|TEST: The signal disposition was set to SIG_DFL
520|0 1 458769 1 5| before delivery
520|0 1 1376263 3 1|TEST: Process terminated due to SIGSEGV
220|0 1 0 16:11:26|PASS
410|0 26 1 16:11:26|IC EndTest Output
400|0 26 1 16:14:13|IC Start
200|0 1 16:14:13|TP Start
520|0 1 4915214 1 1|SPEC1170TESTSUITE CASE 26
520|0 1 4915214 1 2|If the implementation does not inhibit enforcement of
520|0 1 4915214 1 3|limits for the resource RLIMIT_AS:
520|0 1 4915214 1 4|When the size of the stack for the calling process
520|0 1 4915214 1 5|causes the size of the total available memory for the
520|0 1 4915214 1 6|calling process to exceed the limit set by a call to
520|0 1 4915214 1 7|int setrlimit(int resource, const struct rlimit *rlp)
520|0 1 4915214 1 8|for resource RLIMIT_AS and the process is blocking or
520|0 1 4915214 1 9|ignoring SIGSEGV, or is catching SIGSEGV and has not
520|0 1 4915214 1 10|made arrangements to use an alternate stack, the
520|0 1 4915214 1 11|disposition of SIGSEGV shall be set to SIG_DFL before
520|0 1 4915214 1 12|it is generated.
520|0 1 1572871 1 1|PREP: Fork a child
520|0 1 720913 1 1|PREP: Save the current limits
520|0 1 720913 1 2|TEST: Set limits with setrlimit
520|0 1 720913 1 3|INFO: Raise succeeded
520|0 1 720913 1 4|PREP: Set up a signal handler for SIGSEGV
520|0 1 720913 1 5|TEST: The signal disposition was set to SIG_DFL
520|0 1 720913 1 6| before delivery
520|0 1 1572871 2 1|ERROR: wait_for: Timed-out waiting for child to exit.
520|0 1 1572871 2 2|ERROR: Process didn't terminate with SIGSEGV
220|0 1 1 16:15:16|FAIL
410|0 26 1 16:15:16|IC EndReview Information
Review Type TSMA Review Start Date null Completed null Status Complete Review Recommendation No Resolution Given Review Response
We recommend this request be refused.
The test referenced above completes in less than 2 seconds on the
slowest test system we have in house (a 25MHz RISC system). The
two timeouts for this test are 60 seconds each.
If you look at the passing journal the submitter includes you can
see that they are requesting these timeouts be increased to more
than 4380 seconds (73 min) total.
We believe that a reasonable test environment should be able to
complete these tests in the time alloted.
Review Type SA Review Start Date null Completed null Status Complete Review Resolution Test Suite Deficiency (TSD) Review Conclusion
This is an agreed Test Suite Deficiency.
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